实验现象：
在本实验中，将工程中的D触发器、JK触发器实例化，对应其真值表，用signal对其进行
检验，利用SignaTap II观察分析波形。
核心代码：
module D( input CLK, input rst_n, input Data, output Q, output Qn);//-----------------------D---------------------------// reg q,qn; always@(posedge CLK) begin if(!rst_n) begin q <= 1'd0; qn <= 1'd1; end else begin q <= Data; qn <= ~Data; end end assign Q = q; assign Qn =qn; //-------------------endmodule-----------------------//endmodule
module J_K( input CLK, input rst_n, input J, input K, output Q, output Qn);//---------------------J_K---------------------------// reg q,qn; always@(posedge CLK) begin if(!rst_n) begin q <= 1'd0; qn <= 1'd1; end else begin case({J,K}) 2'b00: begin q <= q; qn <= qn; end 2'b01: begin q <= 1'd0; qn <= 1'd1; end 2'b10: begin q <= 1'd1; qn <= 1'd0; end 2'b11: begin q <= ~q; qn <= ~qn; end default : begin q <= 1'd0; qn <= 1'd1; end endcase end end assign Q = q; assign Qn = qn; //-------------------endmodule-----------------------//endmodule 实验方法及指导书:
链接： 密码：d2qp